With the rapid development on integrated circuit (IC) manufacturing technology, size of semiconductor in ICs, especially the size of MOS (Metal-oxide-semiconductor) devices, continues to shrink in order to meet the requirements for miniaturization and high-degree-integration of integrated circuits. As the size of the MOS transistor devices decreases continuously, the existing fabrication technology, which uses silicon oxide or silicon oxynitride as the gate dielectric layer, has been challenged. More specifically, transistors with silicon oxide or silicon oxynitride based gate dielectric layer may have certain problems, such as increased leakage current and impurity diffusion, which may affects the threshold voltage of the transistors. Thus, the performance of semiconductor devices based on such transistors may be impacted.
To solve these problems, transistors with high dielectric constant (high-K) metal gate structures have been introduced. By replacing the silicon oxide or silicon oxynitride gate dielectric materials with the high-K materials, the leakage current can be reduced while the size of the semiconductor devices decreases, and the performance of the semiconductor devices can be improved.
FIG. 1 illustrates an existing transistor having a high-K dielectric layer and a metal gate. The transistor includes a first dielectric layer 105 on the surface of a semiconductor substrate 100, and there is an opening (not shown) exposing the surface of the semiconductor substrate 100 in the first dielectric layer 105. The transistor also includes a high-K dielectric layer 101 covering sidewalls and the bottom of the opening, and a metal gate layer 103 on the high-K dielectric layer 103. Further, the transistor also includes a sidewall spacer 104 on the surface of the semiconductor substrate at both sides of high-K dielectric layer 101 and the metal gate layer 103, and a source region 106a and a drain region 106b in the semiconductor substrate 100 at both sides of the dielectric layer 101, the metal gate layer 103 and the sidewall spacer 104.
After forming the transistor, a back end of line (BEOL) process may be performed. The BEOL process may be used to connect the source region 106a, the drain region 106b, and/or the gate 103 with other semiconductor devices of the ICs.
FIG. 2 illustrates a share contact structure formed by the BEOL process for the existing transistor having a high-K dielectric layer and a metal gate. The share contact structure includes a first conductive via 124 connecting with the surface of the source region 106a, a second conductive via 125 connecting with the surface of the metal gate 103, a conductive layer 126 on the surfaces of the first conductive via 124 and the second conductive via 125. The share contact structure also includes an interlayer dielectric layer 105, and a second dielectric layer 120.
However, the BEOL process for forming the share contact structure of the existing transistor having the high-K dielectric layer 101 and the metal gate layer 103 may be relatively complex, and the production time and cost may be increased. The disclosed device structures, methods and systems are directed to solve one or more problems set forth above and other problems.